This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-395932, filed Dec. 26, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor integrated circuit which has a plurality of power supply levels and causes logic circuits to operate on a very low power supply voltage, and more particularly to a semiconductor integrated circuit provided with an operating circuit and a standby circuit.
2. Description of the Related Art
In recent years, the packing density of semiconductor integrated circuits has increased remarkably. In semiconductor memory devices of the order of gigabits, hundreds of millions of semiconductor elements have been squeezed into a single chip. In a 64-bit microprocessor, millions of to tens of millions of semiconductor elements have been squeezed into a single chip. The improvement of the packing density has been achieved by the miniaturization of elements. In a 1-Gbit DRAM (Dynamic Random Access Memory), MOS transistors with a gate length of 0.15 xcexcm have been used. In a DRAM with a much higher packing density, MOS transistors with a gate length of 0.1 xcexcm or less will be used.
In such very small MOS transistors, the characteristics of the transistors deteriorate due to the generation of hot carriers, or the breakdown of the insulating films occurs due to TDDB (Time-Dependent Dielectric Breakdown). When the concentration of impurities in the substrate region or other regions is increased to suppress a drop in the threshold voltage due to the gate length getting shorter, the junction voltage of the source and drain drops.
To maintain the reliability of these fine elements, it is important to drop the power supply voltage. That is, the generation of hot carriers is prevented by weakening the horizontal electric field between the source and drain, and TDDB is prevented by weakening the vertical electric field between the gate and bulk. Moreover, dropping the power supply voltage decreases the reverse bias applied to the junction between the source and bulk and to the junction between the drain and bulk, thereby coping with a drop in the breakdown voltage.
In mobile information apparatus, whose market has been expanding rapidly in recent years, a lightweight power supply with a high energy density, such as a lithium ion battery, has been widely used. Since the voltage of the lithium ion battery is about 3 V, it is higher than the breakdown voltage of the very small MOS transistor. Therefore, when the lithium ion battery is applied to a circuit using very small transistors, it is necessary to drop its voltage using a DC-DC voltage converter. Since the power consumption of the CMOS circuit used in a logic circuit is proportional to the operating frequency and further proportional to the square of the power supply voltage, lowering the power supply voltage has a significant effect on the decrease of the chip power consumption.
Using mobile information apparatus for a longer time requires a battery with high energy density, a DC-DC converter with high efficiency, and an integrated circuit operating on a low voltage. From the viewpoint of reducing the power consumption of an LSI, it is desirable to use a stepped-down power supply voltage particularly in a microprocessor or baseband LSI which consumes a lot of power.
On the other hand, the mobile information apparatus requires memory elements, such as DRAMs or SRAMs (static random access memories) as well as the logic circuits. In DRAMs, the first subject is to secure a sufficient amount of charge in the cells to increase resistance to errors due to software. In SRAMs, the first subject is to avoid the deterioration of speed when they are operating on low power supply voltages. Therefore, in DRAMs and SRAMs, the power consumption has not been reduced remarkably as found in logic circuits. Presently, elements operating on a power supply voltage of about 1.5 V have been put to practical use.
The power supply voltage of about 1.5 V, however, is much higher than the lowest voltage on which the logic circuits can operate. For this reason, it is conceivable that an LSI including both memory circuits and logic circuits takes and will take a multi-power-supply configuration that supplies various power supply voltages according to each circuit section.
FIG. 1 shows a semiconductor integrated circuit for mobile information apparatus obtained by integrating a memory circuit and a logic circuit into a single chip and the configuration of its power supply. The power supply system is composed of a lithium ion battery 1700 and a DC-DC voltage converter 1701. The semiconductor integrated circuit 1704 is composed of a logic circuit 1702 and an on-chip memory circuit 1703.
More specifically, 3 V from the lithium ion battery 1700 is converted by the DC-DC voltage converter 1700 into a voltage of 0.5 V. The 0.5-V power supply is supplied to the logic circuit 1702. On the other hand, since the on-chip memory circuit 1703 generally needs a power supply voltage of 1.5 to 2.0 V or higher for high speed operation, the 3-V power supply of the lithium ion battery 1700 is supplied to the memory circuit 1703.
With the configuration of FIG. 1, dropping the power supply voltage of the logic circuit from 3 V to about 0.5 V enables the power consumption in operation to be decreased theoretically by about 95%, which reduces the power consumption dramatically.
However, when the power supply voltage of a CMOS circuit operating on a power supply voltage usually ranging from 3 V to 2 V is dropped, since the threshold voltage is high as it is, there arises a problem: the operating speed of the elements decreases or they do not operate.
To solve this problem, the threshold voltage of the MOS transistors is dropped as the power supply voltage drops. For example, to configure a logic circuit operating on a low power supply voltage of 0.5 V, it is necessary to use a MOSFET whose threshold voltage is about 0.1 to 0.15 V in absolute value, about one-third of the threshold voltage of a conventional MOSFET.
With such a low threshold voltage, however, if the S factor that determines the sub-threshold characteristic of, for example, a MOSFET is 100 mV/decade, the leakage current when the MOSFET is off increases significantly by about three orders of magnitude.
Consequently, in an approach of only lowering the power supply, the power consumption in operation can be decreased, whereas the power consumption in the standby state of the apparatus increases significantly. Therefore, the semiconductor integrated circuit is unsuitable for mobile information apparatus as it is.
FIG. 2 shows a known semiconductor integrated circuit configured to overcome the above problem. A power supply voltage converter 1801 converts 3 V from a lithium ion battery 1800 into a voltage of 0.5 V to supply the voltage as low as 0.5 V to a semiconductor integrated circuit 1805 including a logic circuit 1802, thereby reducing the power consumption in operation.
The semiconductor integrated circuit 1805 further comprises a positive power supply voltage generator 1803 and a negative power supply voltage generator 1804 and generates a potential higher than the power supply voltage at the positive power supply voltage generator 1803 and a potential lower than the ground potential at the negative power supply voltage generator 1804. The semiconductor integrated circuit is configured to supply the potentials generated at the voltage generators to the n-well and p-well (now shown) in the logic circuit 1802, thereby making somewhat lower the absolute value of the threshold voltage of the MOSFET in the logic circuit in normal operation to give priority to the operating speed.
With the configuration of FIG. 2, the power consumption can be reduced by making larger the absolute value of the threshold voltage of the MOSFET in the logic circuit in the standby state to decrease the leakage current when the MOSFET is off. By this technique, however, when the voltage is very low as in the 0.5-V power supply, the following problem arises.
In the semiconductor integrated circuit, a charge pump method is generally used in the positive power supply voltage generator 1803 and negative power supply voltage generator 1804. At a very low voltage from, for example, the 0.5-V power supply, an ordinary charge pump method cannot provide a sufficient driving capability to control the well potential. An attempt to increase the driving capability makes the size of the driving MOSFET very large, with the result that the layout area of the voltage generators is larger than that of conventional equivalents.
FIG. 3 is a diagram to help explain a leakage current problem occurring in the off state. In FIG. 3, three kinds of power supply are supplied to a semiconductor integrated circuit 1905. Specifically, a 3-V power supply (VDD) supplied from a nickel-hydrogen battery 1900 and the ground potential (VSS) are connected to a logic circuit 1902 integrated in an on-chip manner in the semiconductor integrated circuit. In addition, a logic circuit power supply VD1 (0.5 V) supplied from a power supply voltage converter 1901 is connected via a pMOSFET 1093 with a high threshold value to a logical circuit power supply line VDDV.
With the configuration of FIG. 3, after the necessary information in the logic circuit is saved in a memory circuit 1904 in the standby state, the gate voltage (/STB) of the pMOSFET 1903 is made VDD and the MOSFET 1903 is brought into the off state. At that time, the leakage current is determined at a very small value by the off characteristic of the pMOSFET 1903 with a high threshold value.
However, since the power supply of the logic circuit 1902 is turned off in the standby state, the procedure for saving the information in the flip-flop of the logic circuit to the memory circuit in advance as described in reference (1 V Power Supply High-Speed Digital Circuit technology with Multi Threshold-Voltage CMOS by S. Mutch et al., 1995 IEEE Journal of Solid State Circuits, Vol. 30 No. 8).
Furthermore, when the logic circuit is large in size and consumes a lot of power, it is necessary to reduce the effect of a drop in the potential due to the ON resistance of the switching transistor pMOSFET 1903 for cutting off current on the circuit stability and speed characteristic of the logic circuit block. This makes the element size of the pMOSFET 1903 very large.
As a result, in addition to the problem of the larger layout area of the circuit that causes the pMOSFET 1903 to switch on and off the power supply, there arises another problem: the power consumption of the driver circuit that drives the gate of the pMOSFET 1903 becomes higher.
Therefore, in the logic circuit, it is necessary to make the low power consumption characteristic in the operating state compatible with the low power consumption characteristic in the standby state. Meeting this requirement by a known proposed method requires a large-scale circuit for switching, making the layout area larger, which leads to an increase in the cost of the semiconductor integrated circuit.
When the logic circuit is large in scale, it takes some time to do switching. To make the switching faster, it is necessary to increase the driving capability of the peripheral driving circuit, which leads to an increase in the power consumption. Moreover, holding the information in the flip-flop of the logic circuit needs an additional circuit, which increases the layout area.
Therefore, in conventional semiconductor integrated circuits for mobile apparatus, there have been strong demands toward realizing a lower power consumption in the operating and standby states, while meeting the operating speed specification.
Methods of making lower the power consumption in the standby state include a well potential control method of generating a voltage higher than the power supply voltage of the logic circuit in the semiconductor integrated circuit and a potential lower than the ground potential on the chip and thereby controlling the well potential and a power supply switching method of constructing a power supply switch using FETs with good off characteristics.
Although these methods are effective in making the standby power consumption lower, use of a very low power supply voltage of about 0.5 V to lower the operating power consumption causes the following problems:
(1) In the well potential control method, the layout area increases to compensate for a decrease in the driving capability due to the lower power supply voltage of the potential generator.
(2) In both of the well potential control method and power supply switch method, the power consumption by the standby control circuit increases in high-speed operation or in the operation of switching to the standby state.
(3) In the power supply switching method, a drop in the power supply voltage due to the power supply switch FET impairs the stability of the circuit and degrades the speed characteristic.
(4) In the standby state in the power supply switching method, an additional circuit for holding data is needed.
These problems make the layout area larger, increases the power consumption, and complicates the design more, which results in an increase in the cost of the integrated circuit.
For this reason, such a semiconductor integrated circuit has been desired as is capable of realizing a lower power consumption in both the operating and standby states in a logic circuit operating on a very low power supply voltage of about 0.5 V without using a complex control circuit.
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a first logic circuit which has a first input terminal and comprises a logic block that essentially connects a first pMIS logic block made up of a pMISFET with a threshold voltage of Vtp1 and a first nMIS inverted-logic block made up of an nMISFET with a threshold voltage of Vtn1 in series between a first power supply with a potential of V1 and a reference potential; a second logic circuit which has a second input terminal connected to the first input terminal and which has the same logic function as that of the first logic circuit and comprises a logic block that essentially connects a second pMIS logic block made up of a pMISFET with a threshold voltage of Vtp2 (Vtp2 less than Vtp1) and a second nMIS inverted-logic block made up of an nMISFET with a threshold voltage of Vtn2 (Vtn2 less than Vtn1) in series between a second power supply with a potential of V2 (V2 less than V1) and the reference potential; and an output switch circuit which intervenes between the first pMIS logic block and the first nMIS inverted-logic block in the first logic circuit and between the second pMIS logic block and the second nMIS inverted-logic block in the second logic circuit and which has a control signal terminal to which a control signal is inputted and an output terminal that switches between an output of the first logic circuit and an output of the second logic circuit according to the control signal.
According to a second aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a first logic circuit which has a first input terminal and comprises a logic block that essentially connects a first pMIS logic block made up of a pMISFET with a threshold voltage of Vtp1 and a first nMIS inverted-logic block made up of an nMISFET with a threshold voltage of Vtn1 in series between a first power supply with a potential of V1 and a reference potential; a second logic circuit with a second input terminal which has a different logic function from that of the first logic circuit and which comprises a logic block that essentially connects a second pMIS logic block made up of a pMISFET with a threshold voltage of Vtp2 (Vtp2 less than Vtp1) and a second nMIS inverted-logic block made up of an nMISFET with a threshold voltage of Vtn2 (Vtn2 less than Vtn1) in series between a second power supply with a potential of V2 (V2 less than V1) and the reference potential; and an output switch circuit which intervenes between the first pMIS logic block and the first nMIS inverted-logic block in the first logic circuit and between the second pMIS logic block and the second nMIS inverted-logic block in the second logic circuit and which has a control signal terminal to which a control signal is inputted and an output terminal that switches between an output of the first logic circuit and an output of the second logic circuit according to the control signal.